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Multi-engine packet classification hardware accelerator

Kennedy, Alan and Liu, Zhen and Wang, Xiaojun and Liu, Bin (2009) Multi-engine packet classification hardware accelerator. In: ICCCN 2009 - 18th International Conference on Computer Communications and Networks, 3-6 August 2009 , San Francisco, CA, USA. ISBN 978-1-4244-4581-3

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Abstract

As line rates increase, the task of designing high performance architectures with reduced power consumption for the processing of router traffic remains important. In this paper, we present a multi-engine packet classification hardware accelerator, which gives increased performance and reduced power consumption. It follows the basic idea of decision-tree based packet classification algorithms, such as HiCuts and HyperCuts, in which the hyperspace represented by the ruleset is recursively divided into smaller subspaces according to some heuristics. Each classification engine consists of a Trie Traverser which is responsible for finding the leaf node corresponding to the incoming packet, and a Leaf Node Searcher that reports the matching rule in the leaf node. The packet classification engine utilizes the possibility of ultra-wide memory word provided by FPGA block RAM to store the decision tree data structure, in an attempt to reduce the number of memory accesses needed for the classification. Since the clock rate of an individual engine cannot catch up to that of the internal memory, multiple classification engines are used to increase the throughput. The implementations in two different FPGAs show that this architecture can reach a searching speed of 169 million packets per second (mpps) with synthesized ACL, FW and IPC rulesets. Further analysis reveals that compared to state of the art TCAM solutions, a power savings of up to 72% and an increase in throughput of up to 27% can be achieved.

Item Type:Conference or Workshop Item (Paper)
Event Type:Conference
Refereed:Yes
Uncontrolled Keywords:computer networks; decision trees; field programmable gate arrays; pattern classification; random-access storage; telecommunication network routing; tree data structures;
Subjects:Engineering > Telecommunication
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Published in:2009 Proceedings of 18th International Conference on Computer Communications and Networks. . Institute of Electrical and Electronics Engineers. ISBN 978-1-4244-4581-3
Publisher:Institute of Electrical and Electronics Engineers
Official URL:http://dx.doi.org/10.1109/ICCCN.2009.5235260
Copyright Information:©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Funders:Irish Research Council for Science Engineering and Technology
ID Code:15526
Deposited On:20 Jul 2010 14:56 by DORAS Administrator. Last Modified 20 Jul 2010 14:56

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