Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M.
(2000)
Power-constrained block-test list scheduling.
In: RSP 2000 - 11th International Workshop on Rapid System Prototyping, 21-23 June 2000, Paris, France.
ISBN 0-7695-0668-2
A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency, having assigned power dissipation limits. Moreover, the algorithm features a power dissipation balancing provision. Test scheduling examples are discussed, highlighting further research steps towards an efficient system-level test scheduling algorithm
Metadata
Item Type:
Conference or Workshop Item (Paper)
Event Type:
Conference
Refereed:
Yes
Uncontrolled Keywords:
integrated circuit design; integrated circuit testing; list processing; logic design; power utilisation; processor scheduling;
Proceedings of the 11th International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.
.
Institute of Electrical and Electronics Engineers. ISBN 0-7695-0668-2