A low complexity hardware architecture for motion estimation
Larkin, Daniel, Muresan, Valentin and O'Connor, Noel E.ORCID: 0000-0002-4033-9135
(2006)
A low complexity hardware architecture for motion estimation.
In: ISCAS 2006 - IEEE International Symposium on Circuits and Systems, 21-24 May 2006, Kos, Greece.
This paper tackles the problem of accelerating motion estimation for video processing. A novel architecture using binary data is proposed, which attempts to reduce power consumption. The solution exploits redundant operations in the sum of absolute differences (SAD) calculation, by a mechanism known as early termination. Further data redundancies are exploited by using a run length coding addressing scheme, where access to pixels which do not contribute to the final SAD value is minimised. By using these two techniques operations and memory accesses are reduced by 93.29% and 69.17% respectively relative to a systolic array implementation.
Metadata
Item Type:
Conference or Workshop Item (Paper)
Event Type:
Conference
Refereed:
Yes
Uncontrolled Keywords:
motion estimation; runlength codes; systolic arrays; video signal processing;