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A three-stage ATM switch with cell-level path allocation

Collier, Martin (1997) A three-stage ATM switch with cell-level path allocation. IEEE Transactions on Communications, 45 (6). pp. 701-709. ISSN 0090-6778

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A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described.

Item Type:Article (Published)
Uncontrolled Keywords:asynchronous transfer mode; broadband networks; multistage interconnection networks; parallel algorithms; telecommunication network routing;
Subjects:Engineering > Telecommunication
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Publisher:Institute of Electrical and Electronics Engineers
Official URL:
Copyright Information:©1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
ID Code:15509
Deposited On:19 Jul 2010 14:23 by DORAS Administrator. Last Modified 19 Jul 2010 14:23

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