Browse DORAS
Browse Theses
Search
Latest Additions
Creative Commons License
Except where otherwise noted, content on this site is licensed for use under a:

A combined tree growing technique for block-test scheduling under power constraints

Muresan, Valentin and Wang, Xiaojun and Muresan, Valentina and Vladutiu, M. (2001) A combined tree growing technique for block-test scheduling under power constraints. In: ISCAS 2001 - IEEE International Symposium on Circuits and Systems, 6-9 May 2001, Sydney, NSW, Australia. ISBN 0-7803-6685-9

Full text available as:

[img]
Preview
PDF - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
508Kb

Abstract

A tree growing technique is used here together with classical scheduling algorithms in order to improve the test concurrency having assigned power dissipation limits. First of all, the problem of unequal-length block-test scheduling under power dissipation constraints is modeled as a tree growing problem. Then a combination of list and force-directed scheduling algorithms is adapted to tackle it. The goal of this approach is to achieve rapidly a test scheduling solution with a near-optimal test application time. This is initially achieved with the list approach. Then the power dissipation distribution of this solution is balanced by using a force-directed global priority function. The force-directed priority function is a distribution-graph based global priority function. A constant additive model is employed for power dissipation analysis and estimation. Based on test scheduling examples, the efficiency of this approach is discussed as compared to the other approaches.

Item Type:Conference or Workshop Item (Paper)
Event Type:Conference
Refereed:Yes
Uncontrolled Keywords:VLSI; automatic testing; integrated circuit testing; low-power electronics; scheduling;
Subjects:Engineering > Engineering education
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Published in:Proceedings of the 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196). . Institute of Electrical and Electronics Engineers. ISBN 0-7803-6685-9
Publisher:Institute of Electrical and Electronics Engineers
Official URL:http://dx.doi.org/10.1109/ISCAS.2001.922033
Copyright Information:©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
ID Code:15534
Deposited On:21 Jul 2010 12:12 by DORAS Administrator. Last Modified 21 Jul 2010 12:12

Download statistics

Archive Staff Only: edit this record