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Power constrained test scheduling in system-on-chip design

Gao, Liang (2004) Power constrained test scheduling in system-on-chip design. Master of Engineering thesis, Dublin City University.

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Abstract

With the development of VLSI technologies, especially with the coming of deep sub-micron semiconductor process technologies, power dissipation becomes a critical factor that cannot be ignored either in normal operation or in test mode of digital systems. Test scheduling has to take into consideration of both test concurrency and power dissipation constraints. For satisfying high fault coverage goals with minimum test application time under certain power dissipation constraints, the testing of all components on the system should be performed in parallel as much as possible. The main objective of this thesis is to address the test-scheduling problem faced by SOC designers at system level. Through the analysis of several existing scheduling approaches, we enlarge the basis that current approaches based on to minimize test application time and propose an efficient and integrated technique for the test scheduling of SOCs under power-constraint. The proposed merging approach is based on a tree growing technique and can be used to overlay the block-test sessions in order to reduce further test application time. A number of experiments, based on academic benchmarks and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed approaches.

Item Type:Thesis (Master of Engineering)
Date of Award:2004
Refereed:No
Supervisor(s):Wang, Xiaojun
Uncontrolled Keywords:system-on-chip; SOC; VSLI; very large scale integration; power constraints; power dissipation
Subjects:Engineering > Electronic engineering
Engineering > Microelectronics
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Use License:This item is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 3.0 License. View License
ID Code:17340
Deposited On:30 Aug 2012 11:22 by Fran Callaghan. Last Modified 30 Aug 2012 11:22

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