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Efficient hardware architectures for MPEG-4 core profile

Larkin, Daniel and Kinane, Andrew and Muresan, Valentin and O'Connor, Noel E. (2005) Efficient hardware architectures for MPEG-4 core profile. In: IMVIP 2005 - 9th Irish Machine Vision and Image Processing Conference, 30-31 August 2005, Belfast, Northern Ireland.

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Abstract

Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile algorithms, namely; texture motion estimation (TME), binary motion estimation (BME)and the shape adaptive discrete cosine transform (SA-DCT). The proposed ME designs may also be used for H.264, since both architectures can handle variable block sizes. Both ME architectures employ early termination techniques that reduce latency and save needless memory accesses and power consumption. They also use a pixel subsampling technique to facilitate parallelism, while balancing the computational load. The BME datapath also saves operations by using Run Length Coded (RLC) pixel addressing. The SA-DCT module has a re-configuring multiplier-less serial datapath using adders and multiplexers only to improve area and power. The SA-DCT packing steps are done using a minimal switching addressing scheme with guarded evaluation. All three modules have been synthesised targeting the WildCard-II FPGA benchmarking platform adopted by the MPEG-4 Part9 reference hardware group.

Item Type:Conference or Workshop Item (Paper)
Event Type:Conference
Refereed:Yes
Subjects:Computer Science > Digital video
DCU Faculties and Centres:Research Initiatives and Centres > Centre for Digital Video Processing (CDVP)
Publisher:School of Computer Science, Queens University Belfast
Use License:This item is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 3.0 License. View License
Funders:Enterprise Ireland
ID Code:354
Deposited On:18 Mar 2008 by DORAS Administrator. Last Modified 05 May 2010 16:27

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