An efficient hardware architecture for a neural network activation function generator
Larkin, Daniel and Kinane, Andrew and Muresan, Valentin and O'Connor, Noel E. (2006) An efficient hardware architecture for a neural network activation function generator. In: ISNN 2006 - International Symposium on Neural Networks, 29-31 May 2006, Chengdu, China. ISBN 978-3-540-34482-7
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This paper proposes an efficient hardware architecture for a function generator suitable for an artificial neural network (ANN). A spline-based approximation function is designed that provides a good trade-off between accuracy and silicon area, whilst also being inherently scalable and adaptable for numerous activation functions. This has been achieved by using a minimax polynomial and through optimal placement of the approximating polynomials based on the results of a genetic algorithm. The approximation error of the proposed method compares favourably to all related research in this field. Efficient hardware multiplication circuitry is used in the implementation, which reduces the area overhead and increases the throughput.
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