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An efficient hardware architecture for a neural network activation function generator

Larkin, Daniel and Kinane, Andrew and Muresan, Valentin and O'Connor, Noel E. (2006) An efficient hardware architecture for a neural network activation function generator. In: ISNN 2006 - International Symposium on Neural Networks, 29-31 May 2006, Chengdu, China. ISBN 978-3-540-34482-7

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Abstract

This paper proposes an efficient hardware architecture for a function generator suitable for an artificial neural network (ANN). A spline-based approximation function is designed that provides a good trade-off between accuracy and silicon area, whilst also being inherently scalable and adaptable for numerous activation functions. This has been achieved by using a minimax polynomial and through optimal placement of the approximating polynomials based on the results of a genetic algorithm. The approximation error of the proposed method compares favourably to all related research in this field. Efficient hardware multiplication circuitry is used in the implementation, which reduces the area overhead and increases the throughput.

Item Type:Conference or Workshop Item (Paper)
Event Type:Conference
Refereed:Yes
Additional Information:The original publication is available at www.springerlink.com
Subjects:Computer Science > Computer networks
Computer Science > Algorithms
DCU Faculties and Centres:Research Initiatives and Centres > Centre for Digital Video Processing (CDVP)
Published in:Advances in Neural Networks - ISNN 2006. Lecture Notes in Computer Science 3973. Springer Berlin / Heidelberg. ISBN 978-3-540-34482-7
Publisher:Springer Berlin / Heidelberg
Official URL:http://dx.doi.org/10.1007/11760191_192
Use License:This item is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 3.0 License. View License
Funders:Enterprise Ireland
ID Code:456
Deposited On:21 May 2008 by DORAS Administrator. Last Modified 05 May 2010 14:38

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