This paper proposes a novel method for the analysis and simulation of integrated circuits (ICs) with the potential to greatly shorten the IC design cycle. The circuits are assumed to be subjected to input signals that have widely separated rates of variation, e.g., in communication systems, an RF carrier modulated by a low-frequency information signal. The proposed technique involves two stages. Initially, a particular order result for the circuit response is obtained using a multiresolution collocation scheme involving cubic spline wavelet decomposition. A more accurate solution is then obtained by adding another layer to the wavelet series approximation. However, the novel technique presented here enables the reuse of results acquired in the first stage to obtain the second-stage result. Therefore, vast gains in efficiency are obtained. Furthermore, a nonlinear model-order reduction technique can readily be used in both stages making the calculations even more efficient. Results will highlight the efficacy of the proposed approach