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The left edge algorithm in block test scheduling under power constraints

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) The left edge algorithm in block test scheduling under power constraints. In: ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, 28-31 May 2000, Geneva, Switzerland. ISBN 0-7803-5482-6

Abstract
A left-edge algorithm approach is proposed in this paper to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the left-edge algorithm in order to improve the test concurrency under power dissipation limits. Test scheduling examples and experiments are discussed highlighting further research directions toward an efficient system-level test scheduling algorithm
Metadata
Item Type:Conference or Workshop Item (Paper)
Event Type:Conference
Refereed:Yes
Uncontrolled Keywords:VLSI; automatic testing; integrated circuit testing; scheduling;
Subjects:Engineering > Electronic engineering
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Published in: ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. . Institute of Electrical and Electronics Engineers. ISBN 0-7803-5482-6
Publisher:Institute of Electrical and Electronics Engineers
Official URL:http://dx.doi.org/10.1109/ISCAS.2000.857102
Copyright Information:©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
ID Code:15535
Deposited On:21 Jul 2010 11:36 by DORAS Administrator . Last Modified 19 Jul 2018 14:51
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