The left edge algorithm in block test scheduling under power constraints
Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M.
(2000)
The left edge algorithm in block test scheduling under power constraints.
In: ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, 28-31 May 2000, Geneva, Switzerland.
ISBN 0-7803-5482-6
A left-edge algorithm approach is proposed in this paper to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the left-edge algorithm in order to improve the test concurrency under power dissipation limits. Test scheduling examples and experiments are discussed highlighting further research directions toward an efficient system-level test scheduling algorithm
ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century.
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Institute of Electrical and Electronics Engineers. ISBN 0-7803-5482-6