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Power-constrained block-test list scheduling

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) Power-constrained block-test list scheduling. In: RSP 2000 - 11th International Workshop on Rapid System Prototyping, 21-23 June 2000, Paris, France. ISBN 0-7695-0668-2

A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency, having assigned power dissipation limits. Moreover, the algorithm features a power dissipation balancing provision. Test scheduling examples are discussed, highlighting further research steps towards an efficient system-level test scheduling algorithm
Item Type:Conference or Workshop Item (Paper)
Event Type:Conference
Uncontrolled Keywords:integrated circuit design; integrated circuit testing; list processing; logic design; power utilisation; processor scheduling;
Subjects:Engineering > Electronic engineering
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Published in: Proceedings of the 11th International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype. . Institute of Electrical and Electronics Engineers. ISBN 0-7695-0668-2
Publisher:Institute of Electrical and Electronics Engineers
Official URL:http://dx.doi.org/10.1109/IWRSP.2000.855220
Copyright Information:©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
ID Code:15536
Deposited On:22 Jul 2010 09:13 by DORAS Administrator . Last Modified 19 Jul 2018 14:51

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