Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M.
(2000)
Power-constrained block-test list scheduling.
In: RSP 2000 - 11th International Workshop on Rapid System Prototyping, 21-23 June 2000, Paris, France.
ISBN 0-7695-0668-2
Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M.
(2000)
The left edge algorithm in block test scheduling under power constraints.
In: ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, 28-31 May 2000, Geneva, Switzerland.
ISBN 0-7803-5482-6
This list was generated on Sat Dec 9 17:54:17 2023 UTC.