Login (DCU Staff Only)
Login (DCU Staff Only)

DORAS | DCU Research Repository

Explore open access research and scholarly works from DCU

Advanced Search

Examination of solder bump reflow process and copper metallisation process induced stress distribution in silicon substrates using synchrotron x-ray topography, micro-raman spectroscopy and finite element modelling

Kanatharana, Jarujit (2003) Examination of solder bump reflow process and copper metallisation process induced stress distribution in silicon substrates using synchrotron x-ray topography, micro-raman spectroscopy and finite element modelling. PhD thesis, Dublin City University.

Abstract
Due to the fact that semiconductor devices have decreased significantly in geometry and increased enormously in electronic design complication, flip-chip packaging technology was launched to increase input/output (I/O) count, improve electrical performance, reduce packaging size, and to be cost effective. The Intel®Pentium®III microprocessor uses the popular ball grid array (BGA) packaging technique. The ball grid array (BGA) is one o f the most common flip-chip, packaging techniques used for microprocessor applications. However, mechanical stresses induced by the flip-chip process are a major concern for the reliability of such devices. In addition, Copper (Cu) is becoming the interconnect metal of choice and is rapidly replacing Aluminium alloys (Al/Cu) in the Integrated Circuit (IC) industry. However, mechanical reliability issues, such as those related to thermal strain are also a major concern. The aim of this thesis is to employ the application of white beam synchrotron x-ray topography (WBSXRT), micro-Raman spectroscopy (MRS) and Finite Element Modeling (FEM) to investigate the spatial extent of strain fields imposed on the underlying silicon substrate for microelectronic packaging of Intel®Pentium®III microprocessors due to the lead-tin solder bump process for BGA packaging, and to evaluate and compare stress distributions in Si wafers due to the electroless Cu interconnect process with varying geometrical line width in IC processing and compare with the sputtered Cu interconnect technique. In the case of the lead-tin solder bump process, large area and section back-reflection SXRT images were taken before and after a simulation of the reflow process at 350°C in atmosphere. The effects of strain imposed by the overlying bump structures in these x-ray topographs have been observed principally via orientational contrast. The estimated magnitudes of stress, I ixy I, imposed on the underlying silicon were calculated to be of the order of 100 MPa. A simulation of the orientational contrast at the edge of bump was performed based on the kinematical theory of x-ray diffraction. The degree of lattice distortion is well fitted to the topographs of the post-reflow sample. The spatial strain in the underlying silicon was relieved dramatically after the lead bumps were removed from the wafer, which confirms that the solder bump formation is indeed a major source of strain in the underlying Si. Micro-Raman Spectroscopy (MRS) is used to confirm the strain fields in the Si due to the reflow process. For /ra-reflowed samples, an approximate uniaxial compressive stress (Gxx) of 200 MPa is developed near the edge o f the under bump metallisation (UBM). However, a tensile stress (CTxx) up to -300 MPa is found for /?astf-reflowed samples. Two-dimensional (2-D) plane strain Finite Element Modelling (FEM) has also been performed. The magnitudes and spatial distribution of the stresses after the reflow process are in good agreement with the SXRT and MRS results. In case of the Cu metallization, 100 nm of Ti is used as a barrier layer and 20 nm of sputtered Cu is used as a seed layer. Electroless and sputtered Cu were subsequently deposited on patterned Si wafers with 4, 6, 8, 10, 20, 40, 60 and 100 ¿im line widths using a lift-off patterning and single damascene pattern. The presence of distinct orientational contrast observed in section topographs suggests that the strain fields in the Si substrate reach values as high as ca. 100 MPa nears the metal edge. The stress magnitudes in the underlying Si as a function of individual line widths were measured using MRS. Compressive stresses of -100 MPa were found in the Si wafer near the line edges when the width is less than 10\im. The stresses changed to tensile with a magnitude of the order of 100 MPa at metal widths of 10-60 [im and decreased to -5 0 MPa for 100 ¿im widths. The FEM analysis confirmed this tendency. Large area back-reflection WBSXRT revealed that strain fields in the Si due to the Cu metallisation were relieved when the sample was heated to 100°C. Subsequently, the stress increases again when the sample was heated up to 400°C. When the samples are returned to room temperature, the MRS data confirms that the strain in the Si near the metal edges become more compressive than in the unannealed case. X-ray diffraction (XRD) data confirms the generation of new material phases after the heat treatment.
Metadata
Item Type:Thesis (PhD)
Date of Award:2003
Refereed:No
Supervisor(s):McNally, Patrick J.
Uncontrolled Keywords:Silicon Defects; Microprocessors Design and construction; Flip chip technology
Subjects:Engineering > Electronic engineering
DCU Faculties and Centres:DCU Faculties and Schools > Faculty of Engineering and Computing > School of Electronic Engineering
Use License:This item is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 3.0 License. View License
ID Code:17941
Deposited On:24 Apr 2013 13:17 by Celine Campbell . Last Modified 24 Apr 2013 13:17
Documents

Full text available as:

[thumbnail of Jarujit_Kanatharana.pdf]
Preview
PDF - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
12MB
Downloads

Downloads

Downloads per month over past year

Archive Staff Only: edit this record