Modern video coding algorithms are becoming increasingly complex with the result that single general purpose processors are incapable of meeting the computational power required for real time implementation. The coding algorithms are continuously evolving therefore, any multiprocessor solution must not only possess the necessary computational power but must also be flexible enough to adapt to any modifications in the algorithms. This report presents a possible multiprocessor solution with specific reference to the DCU object-based analysis-synthesis coder. Firstly, an abstract model of the multiprocessor system is defined. The model is based on the dual requirements of computational power and flexibility. An analysis of the DCU coding algorithm is performed in order to refine the basic model by identifying potential realisation options that optimise coder performance. A reciprocal relationship exists whereby hardware constraints require modification of the algorithm. Any modifications are outlined and their effect on overall coder performance is investigated. Computational power costs are given for an implementation based on TMS320C30 DSPs. From experimental results it is shown that, despite the complexity of the coding algorithm, real time operation is possible. A decoder based on a single TMS320C30 has been developed that is capable of operating at up to 8 Hz.