Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modeling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the charactersation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process