2001

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2001) A combined tree growing technique for block-test scheduling under power constraints. In: ISCAS 2001 - IEEE International Symposium on Circuits and Systems, 6-9 May 2001, Sydney, NSW, Australia. ISBN 0-7803-6685-9

2000

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) A comparison of classical scheduling approaches in power-constrained block-test scheduling. In: International Test Conference 2000, 3-5 October 2000, Atlantic City, NJ, USA. ISBN 0-7803-6546-1

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. In: ATS 2000 - 9th Asian Test Symposium, 4-6 December 2000, Taipei, Taiwan. ISBN 0-7695-0887-1

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) Power-constrained block-test list scheduling. In: RSP 2000 - 11th International Workshop on Rapid System Prototyping, 21-23 June 2000, Paris, France. ISBN 0-7695-0668-2

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) The left edge algorithm in block test scheduling under power constraints. In: ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, 28-31 May 2000, Geneva, Switzerland. ISBN 0-7803-5482-6