Thermal processing steps used during the production of packaged integrated circuits can lead to severe thermomechanical stresses. In addition, the process of bonding wires to contact pads can also lead to strain field generation. A feasibility study using the application of white beam synchrotron x-ray topography to packaged erasable programmable read-only memory (EPROM) Si integrated circuits (ICs) has been undertaken in order to produce maps of the strain fields induced by such processing steps. This technique provides depth-resolved mapping with spatial resolutions currently in the region of 5-10 μm throughout the entire mapping volume. Furthermore, the use of different experimental geometries allows the user to nondestructively probe the strain fields present at the wafer surface right through to the back side.