Larkin, Daniel, Muresan, Valentin and O'Connor, Noel E. ORCID: 0000-0002-4033-9135 (2006) A low complexity hardware architecture for motion estimation. In: ISCAS 2006 - IEEE International Symposium on Circuits and Systems, 21-24 May 2006, Kos, Greece.

Kinane, Andrew, Muresan, Valentin and O'Connor, Noel E. (2006) Towards an optimised VLSI design algorithm for the constant matrix multiplication problem. In: ISCAS 2006 - IEEE International Symposium on Circuits and Systems, 21-24 May 2006, Kos, Greece.

Larkin, Daniel, Kinane, Andrew, Muresan, Valentin and O'Connor, Noel E. ORCID: 0000-0002-4033-9135 (2006) An efficient hardware architecture for a neural network activation function generator. In: ISNN 2006 - International Symposium on Neural Networks, 29-31 May 2006, Chengdu, China. ISBN 978-3-540-34482-7

Kinane, Andrew, Muresan, Valentin and O'Connor, Noel E. ORCID: 0000-0002-4033-9135 (2006) Optimisation of constant matrix multiplication operation hardware using a genetic algorithm. In: EvoHOT 2006 - 3rd European Workshop on Evolutionary Computation in Hardware Optimisation, 10-12 April 2006, Budapest, Hungary. ISBN 978-3-540-33237-4

Kinane, Andrew, Casey, Alan, Muresan, Valentin and O'Connor, Noel E. (2005) FPGA-based conformance testing and system prototyping of an MPEG-4 SA-DCT hardware accelerator. In: FPT 2005 - IEEE 2005 International Conference on Field-Programmable Technology, 11-14 Dec. 2005, Singapore.

Larkin, Daniel, Kinane, Andrew, Muresan, Valentin and O'Connor, Noel E. ORCID: 0000-0002-4033-9135 (2005) Efficient hardware architectures for MPEG-4 core profile. In: IMVIP 2005 - 9th Irish Machine Vision and Image Processing Conference, 30-31 August 2005, Belfast, Northern Ireland.

O'Connor, Noel E. ORCID: 0000-0002-4033-9135, Muresan, Valentin, Kinane, Andrew, Larkin, Daniel, Marlow, Seán and Murphy, Noel (2003) Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview. In: WIAMIS 2003 - 4th Workshop on Image Analysis for Multimedia Interactive Service, 9-11 April 2003, London, UK.

Muresan, Valentin, O'Connor, Noel E. ORCID: 0000-0002-4033-9135, Murphy, Noel, Marlow, Seán and McGrath, Stephen (2002) Low power techniques for video compression. In: ISSC 2002 - Irish Signals and Systems Conference, 25-26 June 2002, Cork, Ireland.

Muresan, Valentin (2002) Block-level test scheduling under power dissipation constraints. PhD thesis, Dublin City University.

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2001) A combined tree growing technique for block-test scheduling under power constraints. In: ISCAS 2001 - IEEE International Symposium on Circuits and Systems, 6-9 May 2001, Sydney, NSW, Australia. ISBN 0-7803-6685-9

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) A comparison of classical scheduling approaches in power-constrained block-test scheduling. In: International Test Conference 2000, 3-5 October 2000, Atlantic City, NJ, USA. ISBN 0-7803-6546-1

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. In: ATS 2000 - 9th Asian Test Symposium, 4-6 December 2000, Taipei, Taiwan. ISBN 0-7695-0887-1

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) Power-constrained block-test list scheduling. In: RSP 2000 - 11th International Workshop on Rapid System Prototyping, 21-23 June 2000, Paris, France. ISBN 0-7695-0668-2

Muresan, Valentin, Wang, Xiaojun, Muresan, Valentina and Vladutiu, M. (2000) The left edge algorithm in block test scheduling under power constraints. In: ISCAS 2000 - IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, 28-31 May 2000, Geneva, Switzerland. ISBN 0-7803-5482-6