Traditional Si CMOS scaling following Moore’s Law is becoming increasingly difficult as physical limits are approached at sub-20 nm nodes and beyond. A significant issue is the limited charge carrier mobility in Si, and so new channel materials that carry relatively higher mobility carriers have been used, such as strained Si. Other materials such as III-V and germanium (Ge) are currently under consideration for replacing the conventional Si channel for future generations of low power and high speed electronics. However, challenges still remain with the realisation of high quality III-V material on Si for CMOS devices fabrication because the tolerance to dislocations is very low (<105 cm-2). In order to overcome this problem, a non-destructive X-ray characterisation routine which can be used to effectively help III-V growers identify various issues associated with heteroepitaxial growth of III-V materials and which delivers useful experimental feedback to growers for material quality optimisation has been designed. The feasibility of this routine has been demonstrated through the characterisation of a series of deliberately fabricated “problematic” heteroepitaxial GaAs materials. According to industry experts, the future of modern nanoelectronics may well also depend on a second trend, which is the implementation of diverse functionality within modern ICs. This “More than Moore” (MtM) approach will be realised through the manufacture of complex Systems on Chip (SoC) and Systems in Package (SiP), evolving towards fully three-dimensional ICs (3-D ICs). However, progress in this direction is hampered by the lack of a compelling metrology in order to measure non-destructively and in situ the process induced warpage, strain and other defects inside silicon die, a problem which has been highlighted by the International Technology Roadmap for Semiconductors (ITRS). Therefore, the second aim of this thesis has been the development of a novel laboratory-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) in order to address this major stumbling block in the development of MtM integrated circuit technology.